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INTEGRATED CIRCUITS
PCK2020 CK00 (100/133MHz) spread spectrum differential system clock generator
Product specification Supersedes data of 2000 Jul 25 2000 Nov 13
Philips Semiconductors
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
FEATURES
* 3.3 V operation * Four differential CPU clock pairs * Ten PCI clocks at 3.3 V * Four 66 MHz clocks at 3.3 V * Two 48 MHz clocks at 3.3 V * Two 14.318 MHz reference clocks * 100 or 133 MHz operation * Power management control pins * CPU clock skew less than 200 ps cycle-to-cycle * CPU clock skew less than 150 ps pin-to-pin * 1.5 ns to 3.5 ns delay on PCI pins * Spread Spectrum capability
DESCRIPTION
The PCK2020 is a clock synthesizer/driver for a Pentium III and other similar processors. The PCK2020 has four differential pair CPU current source outputs, two Mref clock outputs running at 1/2 the CPU clock frequency depending on the state of SEL133/100 pin and four 3V66 clocks running at 66 MHz. There are ten PCI clock outputs running at 33 MHz and two 48 MHz clocks. Finally, there are two 3.3 V reference clocks at 14.318 MHz. All clock outputs meet Intel's drive strength, rise/fall times, jitter, accuracy, and skew requirements. The part possesses a dedicated power-down input pin for power management control. This input is synchronized on-chip and ensures glitch-free output transitions.
PIN CONFIGURATION
VSSRef Ref0/MultSel0 Ref1/MultSel1 VDD3.3Ref XTAL_IN XTAL_OUT VSSPCI PCICLK0 PCICLK1 1 2 3 4 5 6 7 8 9 56 VDD3.3M 55 3VMref 54 3VMref_b 53 VSSM 52 SPREAD 51 CPUCLK0 50 CPUCLK0 49 VDD3.3CPU 48 CPUCLK1 47 CPUCLK1 46 VSSCPU 45 CPUCLK2 44 CPUCLK2 43 VDD3.3CPU 42 CPUCLK3 41 CPUCLK3 40 VSSCPU 39 I_REF 38 VDD3.3Core 37 VSSCore 36 VDD3.3 35 3V66_0 34 3V66_1 33 VSS 32 VSS 31 3V66_2 30 3V66_3 29 VDD3.3
VDD3.3PCI 10 PCICLK2 11 PCICLK3 12 VSSPCI 13 PCICLK4 14 PCICLK5 15 VDD3.3PCI 16 PCICLK6 17 PCICLK7 18 VSSPCI 19 PCICLK8 20 PCICLK9 21 VDD3.3PCI 22 SEL100/133 23 VSSUSB 24 48MHz0/SelA 25 48MHz1/SelB 26 VDD3.3USB 27 PWRDWN 28
SW00577
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP TEMPERATURE RANGE (C) 0 to +70 ORDER CODE PCK2020 DL DRAWING NUMBER SOT371-1
Intel and Pentium are registered trademarks of Intel Corporation.
2000 Nov 13
2
853-2209 25006
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
PIN DESCRIPTION
PIN NUMBER 1 2, 3 4 5 6 7, 13, 19 8, 9, 11, 12, 14, 15, 17, 18, 20, 21 10, 16, 22 23 24 25, 26 27 28 29, 36 30, 31, 34, 35 32, 33 37 38 39 40, 46 41, 44, 47, 50 42, 45, 48, 51 43, 49 52 53 54 55 56 SYMBOL VSSRef Ref0/MultSel0 Ref1/MultSel1 VDD3.3Ref XTAL_IN XTAL_OUT VSSPCI PCICLK[0-9] VDD3.3PCI SEL100/133 VSSUSB 48 MHz/SelA 48 MHz/SelB VDD3.3USB PWRDWN VDD3.3 3V66[0-3] VSS VSSCore VDD3.3Core I_REF VSSCPU CPUCLK[0-3] CPUCLK[0-3] VDD3.3CPU SPREAD VSSM 3VMref_b 3VMref VDD3.3M 3.3 V clock outputs running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending on the state of input pin SEL133/100. (Out of phase with 3VMREF output). 3.3 V clock outputs running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending on the state of input pin SEL133/100. 3.3 V power supply Enables spread spectrum mode when held low on differential host outputs, MREF/MREF_B clocks, 66 MHz clocks, and 33 MHz PCI clocks. Asserts low. 3.3 V power supply for analog circuits. This pin controls the reference current for the host pairs. This pin requires a fixed precision resistor tied to ground in order to establish the correct current. 3.3 V fixed 66 MHz CPU clock outputs. Device enters power down mode when held low. Asserts low. 3.3 V fixed 48 MHz clock outputs. During power up, pins functions as latched inputs that enables SELA and SELB prior to the pins being used for output of 3 V at 48 MHz. Part must be clocked to latch data in. Select input pin for enabling 133 MHz or 100 MHz CPU outputs. 3.3 V PCI clock outputs fixed at 33 MHz. Crystal input Crystal output During power up, pins functions as a latched inputs that enables MULTSEL0 and MULTSEL1 prior to the pins being used for output of 3 V at 14.318 MHz. Part must be clocked to latch data in. FUNCTION
2000 Nov 13
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Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
BLOCK DIAGRAM
PWRDWN
X REF [0-1](14.318 MHz)
XIN X 14.318 MHZ OSC USBPLL
XOUT X
PWRDWN
X 48 MHz[0-1] 3 V
X CPUCLK [0-3] SPREAD X SYSPLL PWRDWN X CPUCLK [0-3]
SEL 133/100 X SEL0 X SEL1 X DECODE LOGIC
PWRDWN
X 3V66 [0-3] (66 MHz)
PWRDWN
X 3VMRef
PWRDWN
X PCICLK_F (33 MHz)
PWRDWN X
PWRDWN
X 3VMRef
PWRDWN
X PCICLK_F (33 MHz)
SW00727
2000 Nov 13
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Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
FUNCTION TABLES
SEL 100/133 0 0 0 0 1 1 1 1 SELA 0 0 1 1 0 0 1 1 SELB 0 1 0 1 0 1 0 1 HOST 100 MHz 105 MHz1 200 MHz HI-Z 133 MHz 126.7 MHz1 200 MHz TCLK/2 MREF 50 MHz 52.5 MHz1 50 MHz HI-Z 66.7 MHz 63.3 MHz1 66.7 MHz TCLK/4 3V66 66.7 MHz 70 MHz1 66.7 MHz HI-Z 66.7 MHz 63.3 MHz1 66.7 MHz TCLK/4 3V33 PCI 33.3 MHz 35 MHz1 33.3 MHz HI-Z 33.3 MHz 31.7 MHz1 33.3 MHz TCLK/8 48 MHz 48 MHz 48 MHz N/A HI-Z 48 MHz 48 MHz 48 MHz TCLK/2 REF 14.318 MHz 14.318 MHz N/A HI-Z 14.318 MHz 14.318 MHz 14.318 MHz TCLK
NOTE: 1. These frequencies are for debug and thus can vary a small amount from the values listed at the vendor's discretion. SEL 100/133 0 0 0 0 1 1 1 1
SELA 0 0 1 1 0 0 1 1
SELB 0 1 0 1 0 1 0 1 Active 100 MHz Active 100 MHz - ~5% over-clock 200 MHz, 50 MHz MREF HI-Z all outputs Active 133 MHz Active 133.3 MHz minus ~5 under-clock 200 MHz, 66 MHz MREF Test mode
HOST
POWER DOWN MODE
PWRDWN Asserts low 0 = Active HOST/HOST_BAR HOST = 2*IREF HOST_BAR MREF/MREF_B LOW 3V66 LOW PCI LOW 48 MHz LOW REF OFF 14.318/66 MHz Seeds LOW/(if applicable)
NOTE: 1. The differential outputs should have a voltage forced across them when power down is asserted.
SPREAD SPECTRUM FUNCTION TABLE
SPREAD 1 0 FUNCTION HOST/PCI/3V66/MREF/MREF_B No spread HOST/PCI/3V66/MREF/MREF_B Down spread -0.5% 48 MHz PLL REF/MULTSEL0 REF/MULTSEL1 No spread No spread
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Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
HOST SWING SELECT FUNCTIONS - TABLE 1
MULTSEL0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MULTSEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BOARD IMPEDANCE 60 50 60 50 60 50 60 50 30 25 30 25 30 25 30 25 IREF RREF = 475 1% IREF = -2.32 mA RREF = 475 1% IREF = -2.32 mA RREF = 475 1% IREF = -2.32 mA RREF = 475 1% IREF = -2.32 mA RREF = 475 1% IREF = -2.32 mA RREF = 475 1% IREF = -2.32 mA RREF = 475 1% IREF = -2.32 mA RREF = 475 1% IREF = -2.32 mA RREF = 221 1% IREF = -5 mA RREF = 221 1% IREF = -5 mA RREF = 221 1% IREF = -5 mA RREF = 221 1% IREF = -5 mA RREF = 221 1% IREF = -5 mA RREF = 221 1% IREF = -5 mA RREF = 221 1% IREF = -5 mA RREF = 221 1% IREF = -5 mA IOH IOH = 5*IREF IOH = 5*IREF IOH = 6*IREF IOH = 6REF IOH = 4*IREF IOH = 4*IREF IOH = 7*IREF IOH = 7*IREF IOH = 5*IREF IOH = 5*IREF IOH = 6*IREF IOH = 6*IREF IOH = 4*IREF IOH = 4*IREF IOH = 7*IREF IOH = 7*IREF VOH @ IREF = 2.32 mA 0.71 V 0.59 V 0.85 V 0.71 V 0.56 V 0.47 V 0.99 V 0.82 V 0.75 V 0.62 V 0.90 V 0.75 V 0.60 V 0.50 V 1.05 V 0.84 V
NOTE: 1. In Table 1, the outputs are optimized for the configurations in bold. CONDITIONS IOUT IOUT VDD = 3.3 V VDD = 3.3 V 5% CONFIGURATION All combinations, see Table 1 All combinations, see Table 1 LOAD Nominal test load for given configuration Nominal test load for given configuration MIN. -7% of IOH See Table 1 -12% of IOH See Table 1 MAX. +7% of IOH See Table 1 +12% of IOH See Table 1
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Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VDD3 IIK VI IOK VO IO TSTG PTOT PARAMETER DC 3.3 V supply DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current Storage temperature range Power dissipation per package plastic medium-shrink (SSOP) For temperature range: -40 to +125C above +55C derate linearly with 11.3 mW/K VI < 0 Note 2 VO > VDD or VO < 0 Note 2 VO = 0 to VDD -65 -0.5 50 VDD + 0.5 50 +150 850 CONDITION LIMITS MIN -0.5 MAX +4.6 -50 UNIT V mA V mA V mA C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VDD3 AVDD PARAMETER DC 3.3 V supply voltage DC 3.3 V analog supply voltage Capacitive load on: PCICLK 3V66 48 MHz clock REF MREF, MREF_BAR Reference frequency, oscillator normal value Operating ambient temperature range in free air Must meet PCI 2.1 requirements 1 device load, possible 2 loads 1 device load 1 device load 1 device load 10 10 10 10 10 14.31818 0 30 30 20 20 30 14.31818 +70 pF pF pF pF pF MHz C CONDITIONS LIMITS MIN 3.135 3.135 MAX 3.465 3.465 UNIT V V
CL
fREF Tamb
POWER MANAGEMENT
CONDITION Power-down mode (PWRDWN = 0) Full active 100/133 MHz MAXIMUM 3.3 V SUPPLY CONSUMPTION MAXIMUM DISCRETE CAP LOADS, VDDL= 3.465 V ALL STATIC INPUTS = VDD3 OR VSS 60 mA 250 mA
2000 Nov 13
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Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
DC CHARACTERISTICS
SYMBOL PARAMETER VDD (V) VIH VIL VOH3 HIGH level input voltage LOW level input voltage 3.3 V output HIGH voltage REF, 3V48M, 3V66, MREF, MREF_BAR, 48 MHz 3.3 V output LOW voltage REF, 3V48M, 3V66, MREF, MREF_BAR, 48 MHz 3.3 V output HIGH voltage PCI 3.3 V output LOW voltage PCI PCI, 3V66 3VMREF 3VMREF_BAR output HIGH current 48 MHz, REF , output HIGH current HOST/HOST_BAR _ OUTPUT CURRENT PCI, 3V66 3VMREF 3VMREF_BAR output LOW current 48 MHz, REF , output LOW current HOST/HOST_BAR Input leakage current 3-State output OFF-State current Input pin capacitance Crystal input capacitance Output pin capacitance 13.5 3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 IOH = -1 mA TEST CONDITIONS OTHER LIMITS Tamb = 0C to +70C MIN 2.0 VSS - 0.3 2.0 TYP MAX VDD3 + 0.3 0.8 - V V V UNIT
VOL3 VOHP VOLP
3.135 to 3.465 3.135 to 3.465 3.135 to 3.465 3.135 3.465 3.135 3.465 3.135 3.465 3 135 to 3 465 3.135 3.465 3.135 3.465 VSS = 0.0 3.365 3.465
IOH = 1 mA IOH = -1 mA IOH = 1 mA VOUT = 1.0 V VOUT = 3.135 V VOUT = 1.0 V VOUT = 3.135 V 0.66 V 0.76 V VOUT = 1.95 V VOUT = 0.4 V VOUT = 1.95 V VOUT = 0.4 V Rs = 33.2 Rp = 49.9 0 < VIN < VDD3 VOUT = VDD or GND IO = 0 Type 5 y 12-55 Type 3 y 20-60 Type X1
- 2.4 - -33
0.4 - 0.55
V V V
IO OH
mA -33 -29 -23 -11 -12.7 30 mA 38 29 27 0.0 -5 0.05 5 10 5 22.5 6 mA V A A pF pF pF mA mA
IO OH IO OH
IO OL
y Type 5 12-55 Type 3 y 20-60 Type X1
IO OL VOL II IOZ Cin Cxtal Cout
NOTE: 1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section.
2000 Nov 13
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Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
AC CHARACTERISTICS
VDD3 = 3.3 V -5%; fcrystal = 14.31818 MHz
HOST CLOCK OUTPUTS (SEE FIGURE 1 FOR WAVEFORMS AND FIGURE 6 FOR TEST SETUP)
SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133 MHz MODE MIN TPKP AbsMinPeriod TRISE TFALL TJITTER DUTY CYCLE TSKEW Rise/Fall Matching Vcrossover HOST CLK period Absolute Minimum Host CLK Period HOST CLK rise time HOST CLK fall time HOST CLK cycle-to-cycle jitter Output duty cycle HOST CLK pin-to-pin skew Rise and fall time matching 45% VOH 45 7.5 7.35 175 175 MAX 7.65 N/A 700 700 200 55 150 35% 60% VOH 45% VOH 45 100 MHZ MODE MIN 10.0 9.85 175 175 MAX 10.2 N/A 700 700 200 55 150 35% 60% VOH V ns ns ps ps ps % ps 11, 14, 20 11, 14, 20 11, 15, 20 11, 15, 20 11, 12, 14, 20 11, 14, 20 11, 14, 20 11, 16, 20 11, 14, 20 UNITS NOTES
MREF OUTPUTS
SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133 MHz MODE MIN TPKP TPKH TPKL TRISE TFALL TJITTER DUTY CYCLE MREF period MREF HIGH time MREF LOW time MREF rise time MREF fall time Cycle-to-cycle jitter Output Duty Cycle 45 15.0 5.25 5.05 0.5 0.5 MAX 15.3 N/A N/A 2.0 2.0 250 55 45 100 MHz MODE MIN 20.0 7.5 7.3 0.5 0.5 MAX 20.4 N/A N/A 2.0 2.0 250 55 ns ns ns ns ns ps % 2, 9, 20 5, 10, 20 6, 10, 20 8, 20 8, 20 18, 20 18, 20 UNITS NOTES
3V66 OUTPUTS
SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133 MHz MODE MIN TPKP TPKH TPKL TRISE TFALL TJITTER DUTY CYCLE TSKEW 3V66 period 3V66 HIGH time 3V66 LOW time 3V66 rise time 3V66 fall time Cycle-to-cycle jitter Output Duty Cycle Pin-to-pin skew 45 15.0 5.25 5.05 0.5 0.5 MAX 16.0 N/A N/A 2.0 2.0 300 55 250 45 100 MHz MODE MIN 15.0 5.25 5.05 0.5 0.5 MAX 16.0 N/A N/A 2.0 2.0 300 55 250 ns ns ns ns ns ps % ps 2, 4, 9, 20 5, 10, 20 6, 10, 20 8, 20 8, 20 18, 20 18, 20 20 UNIT NOTES
2000 Nov 13
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Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
PCI OUTPUTS
SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133 MHz MODE MIN TPKP TPKH TPKL TRISE TFALL TJITTER DUTY CYCLE TSKEW PCI period PCI HIGH time PCI LOW time PCI rise time PCI fall time Cycle-to-cycle jitter Output Duty Cycle Pin-to-pin skew 45 30.0 12.0 12.0 0.5 0.5 MAX N/A N/A N/A 2.0 2.0 500 55 500 45 100 MHz MODE MIN 30.0 12.0 12.0 0.5 0.5 MAX N/A N/A N/A 2.0 2.0 500 55 500 ns ns ns ns ns ps % ps 2, 3, 9, 20 5, 10, 20 6, 10, 20 8, 20 8, 20 18, 20 18, 20 18, 20 UNITS NOTES
USB CLOCK OUTPUT, 48 MHz (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL PARAMETER MIN f fD THKL TRISE TFALL TJITTER DUTY CYCLE Frequency, Actual Deviation from 48 MHz 3V48MHZCLK LOW time 3V48MHZCLK rise time 3V48MHZCLK fall time Cycle-to-cycle jitter Output Duty Cycle 45 5.05 1.0 1.0 N/A 4.0 4.0 350 55 45 LIMITS Tamb = 0C to +70C 48 MHz MAX 48.008 +167 5.05 1.0 1.0 N/A 4.0 4.0 350 55 MIN MAX MHz ppm ns ns ns ps % 20 8, 20 8, 20 18, 20 18, 20 UNITS NOTES
REF CLOCK OUTPUT, (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL PARAMETER MIN f THKL THKH TRISE TFALL TJITTER DUTY CYCLE Frequency, Actual REF CLK LOW time REF CLK HIGH time REF CLK rise time REF CLK fall time Cycle-to-cycle jitter Output Duty Cycle 45 31.0 32.0 N/A N/A 36.67 37.5 N/A N/A 1000 55 45 LIMITS Tamb = 0C to +70C 48 MHz MAX 14.318 31.0 32.0 N/A N/A 36.67 37.5 N/A N/A 1000 55 MIN MAX MHz ns ns ns ns ps % 20 20 20 8, 20 8, 20 18, 20 18, 20 UNITS NOTES
ALL OUTPUTS
SYMBOL PARAMETER LIMITS Tamb = 0C to +70C 133 MHz MODE MIN TpZL, tpZH TpLZ, tpZH TSTABLE Output enable delay (all outputs) Output disable delay (all outputs) All clock Stabilization from Power-up 1.0 1.0 MAX 10.0 10.0 3 100 MHz MODE MIN 1.0 1.0 MAX 10.0 10.0 3 ns ns ms 20 20 7, 20 UNITS NOTES
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Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
GROUP OFFSET LIMITS
GROUP 3V66 to PCI OFFSET 1.5-3.5 ns 3V66 leads MEASUREMENT LOADS (LUMPED) 3V66 @ 30 pf PCI @ 30 pf MEASURE POINTS 3V66 @ 1.5 V PCI @ 1.5 V NOTES 19, 20
NOTES: 1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels. 2. Period, jitter, offset and skew measured on rising edge @ 1.25 V for 2.5 V clocks and @ 1.5 V for 3.3 V clocks. 3. The PCI clock is the Host clock divided by four at Host = 133 MHz. PCI clock is the Host clock divided by three at Host = 100 MHz. 4. 3V66 is internal VCO frequency divided by four for Host = 133 MHz. 3V66 clock is internal VCO frequency divided by three at Host = 100 MHz. 5. THKH is measured at 2.0 V for 2.5 V outputs and 2.4 V for 3.3 V outputs as shown in Figure 7. 6. THKL is measured at 0.4 V for all outputs as shown in Figure 7. 7. The time is specified from when VDDQ achieves its normal operating level (typical condition VDDQ = 3.3 V) until the frequency output is stable and operating within specification. 8. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification. 9. The average period over any 1 s period of time must be greater than the minimum specified period. 10. Calculated at minimum edge-rate (1 V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure duty-cycle specification is met. 11. Test load is Rs = 33.2 , Rp = 49.9 . 12. Must be guaranteed in a realistic system environment. 13. Configured for VOH = 0.71 V in a 50 environment. 14. Measured at crossing points. 15. Measured at 20% to 80%. 16. Determined as a fraction of 2* (Trp-Trn)/(Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge. 17. Voltage measure point (Vm = 1.25 V). VDD = 2.5 V. 18. Voltage measure point (Vm = 1.5 V). VDD = 3.3 V. 19. All offsets are to be measured at rising edges. 20. Parameters are guaranteed by design.
2000 Nov 13
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Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
AC WAVEFORMS
VM = 1.25 V @ VDDL and 1.5 V @ VDD3 VX = VOL + 0.3 V VY = VOH -0.3 V VOL and VOH are the typical output voltage drop that occur with the output load.
VI SEL1, SEL0 GND tPLZ tPZL VM
VDDQ2 CPUCLK @133MHz 1.25V VSS
VDD OUTPUT LOW-to-OFF OFF-to-LOW VOL VM VX tPHZ VOH tPZH
VDDQ3 3v66 @66MHz 1.5V VSS CPU leads 3V66 THPOFFSET
OUTPUT HIGH-to-OFF OFF-to-HIGH VSS Outputs enabled
VY VM
SW00569
Outputs disabled
Outputs enabled
Figure 1. Host clock Figure 3. State enable and disable times
COMPONENT MEASUREMENT POINTS 2.5VOLT MEASURE POINTS VOH = 2.0V VDDQ2 VIH = 1.7V 1.25V VIL = 0.7V SYSTEM MEASUREMENT POINTS 3.3VOLT MEASURE POINTS VOH = 2.4V VDDQ3 VIH = 2.0V 1.5V VIL = 0.7V SYSTEM MEASUREMENT POINTS
SW00571
VOL = 0.4V VSS COMPONENT MEASUREMENT POINTS
VOL = 0.4V VSS
SW00570
Figure 2. 3.3 V clock waveforms
2000 Nov 13
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Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
S1 VDD 2RT
CL
500
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 2VDD = VDDQ2 or VDDQ3, DEPENDS ON THE OUTPUT
SW00572
Figure 4. Load circuitry for switching times
PWRDWN
CPUCLK (INTERNAL)
PCICLK (INTERNAL)
PWRDWN
CPUCLK (EXTERNAL) PCICLK (EXTERNAL)
USB (48 MHz)
Figure 5. Power management
2000 Nov 13
13
AA AA AA AA
OSC & VCO
SW00573
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
S1 VDD 2RT
CL
500
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 2VDD = VDDQ2 or VDDQ3, DEPENDS ON THE OUTPUT
SW00574
Figure 6. Host clock measurements
THKP DUTY CYCLE THKH 2.5 V CLOCKING INTERFACE 2.0 V 1.25 V 0.4 V THKL TRISE TFALL TPKP DUTY CYCLE TPKH 3.3 V CLOCKING INTERFACE (TTL) 2.4 V 1.5 V 0.4 V TPKL TRISE TFALL
SW00575
Figure 7. 2.5 V/3.3 V clock waveforms
2000 Nov 13
14
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
2000 Nov 13
15
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum differential system clock generator
PCK2020
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 11-00 Document order number: 9397 750 07818
Philips Semiconductors
2000 Nov 13 16

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